Integrated circuits (IC) are manufactured by forming discrete semiconductor devices on a surface of a semiconductor substrate, such as a silicon (Si) wafer. A multi-level network of interconnect structures is then formed to interconnect the devices. Copper (Cu) is the wiring material of choice for interconnect structures of advanced IC devices having a high circuit density. In addition to superior electrical conductivity, copper is more resistant than aluminum (Al) to electromigration, a phenomenon that may destroy a thin film conductive line during IC operation.
In the semiconductor industry, much effort is spent in developing smaller IC devices with ever-increasing operating speeds. To increase the circuit density, a dual damascene technique may be used during fabrication of the IC devices. Then, to increase the operating speed of such a device, inter-metal dielectric (IMD) layers are formed using materials having dielectric constants less than 4.0. Such materials are generally referred to as low-k materials. The low-k materials generally comprise carbon-doped dielectrics, such as organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), organic polymers, and the like.
An IC device comprises a plurality of interconnect structures that are separated from each other and the substrate by the IMD layers. Such structures are generally fabricated using a dual damascene technique that comprises forming an insulator layer (e.g., IMD layer) into which trenches and openings are etched to pattern the contact vias and the conductive lines. The copper is then used to fill (metallize) the trenches and openings in the IMD layer, forming vias and conductive lines, respectively. During the copper metallization process, an excess amount of copper may be deposited onto the substrate. The excess metal may be removed using a planarization process, e.g., chemical-mechanical polishing (CMP) process. After the planarization process, the next wiring layer may be formed on top of the IMD layer.
One problem with the use of copper in the interconnect structures is its tendency to diffuse into silicon dioxide, silicon and other adjacent dielectric materials. Therefore, barrier layers become increasingly important to prevent copper from diffusing into the dielectric and compromising the integrity of the device. Barrier layers for copper applications are available for inter-dielectric applications. However, many of these barrier layers need an adhesion layer between the copper surface and the barrier layer to prevent the barrier layer from separating. Poor adhesion of the copper to a diffusion barrier results in portions of the copper being undesirably peeled away during polishing. This condition can also render an integrated circuit defective.
When these adhesion layers are formed on the copper surface they can increase the sheet resistance (Rs) of the copper interconnect. Accordingly, there is a need to employ a process of improving the adhesion of CVD copper to a diffusion barrier material surface without significantly increasing the sheet resistance of the underlying copper interconnect. These and other problems are address by the present invention.